ENGINEERING: Principal Engineer for adv. semiconductor process dsgn flow, methodology & automation; SRAM Design Engineer incl timing, power, layout, compiler coding & verification; Design Engineer to verify processor, SOC & memory, analyze root course & MOS VLSI; Technical Manager to lead R&D of OPC simulation SW & model calibrator for manufacture; Sr. Program Manager for 5nm MRAM processing R&D, support. Work site/mail resume to: TSMC Technology, Inc., 2851 Junction Ave, San Jose, CA 95134